1. Field of the Invention
The invention generally relates to a method of fabricating a semiconductor, and more particularly to a method of forming a silicide film composed of refractory metal in self-aligning fashion on a diffusion layer and a gate electrode in a MOS transistor.
2. Description of the Related Art
With demand for a micro-sized and/or highly densified semiconductor device, there has been research and development a ultra-large scale integrated semiconductor device such as a memory device and a logic device has been in accordance with 0.15-0.25 .mu.m design rule. Such ultra-large integration of a semiconductor device requires a reduced width of a gate electrode and a diffusion layer, and a reduced thickness of various layers constituting a semiconductor device.
However, a reduced width of a gate electrode or wirings associated with a gate electrode and a reduced thickness of layers constituting a gate electrode inevitably brings increased wiring resistance, which causes delayed operation in a circuit. Thus, it is quite important in a micro-sized semiconductor device to make a silicide layer composed of refractory metal, which constitutes a part of a gate electrode, have decreased resistance. In particular, technology for forming salicide (self-aligned-silicide) in which titanium is used as refractory metal is indispensable for fabricating a micro-sized insulative gate field effect transistor (hereinafter, referred to simply as "MOS transistor").
With the demand for ultra-large scale integration of a semiconductor device, it is necessary in the MOS transistor to restrict diffusion of impurities in a diffusion layer to thereby depress the short channel effect. As a result, a junction depth in a diffusion layer is made shallower. However, if a surface of the diffusion layer comes in contact with a silicide region, leak current caused by crystal defects is increased with the result of inoperability of switching operation of the MOS transistor. Accordingly, as the junction depth is made shallower in the diffusion layer, it is absolutely necessary for the silicide layer to have a decreased thickness.
Hereinbelow is explained a conventional method of fabricating a MOS transistor having a salicide configuration with reference to FIGS. 1A to 1E, which are cross-sectional views of a transistor, showing respective step of the method.
First, as illustrated in FIG. 1A, a plurality of device isolation insulative films 102 are formed by LOCOS in certain regions on a silicon substrate 101. Then, impurities acting as a channel stopper are ion-implanted, and then a gate insulative film 103 is deposited by thermal oxidation.
Then, a polysilicon film having a thickness of about 150 nm is deposited by CVD over a resultant. Then, impurities such as phosphorus are doped. Then, the polysilicon film is patterned by photolithography and dry-etching into a desired pattern to thereby form a gate electrode 104. Then, a silicon dioxide film is deposited by CVD over a resultant. Subsequently, anisotropic dry etching is carried out, thereby forming a spacer 105 at a sidewall of the gate electrode 104.
Then, impurities such as arsenic (As) and boron (B) are ion-implanted, and subsequently, a resultant is thermally annealed at temperature in the range of 800.degree. C. to 1000.degree. C. to thereby form a diffusion layer 106. If an n-channel MOS transistor is to be fabricated, the diffusion layer including arsenic is formed, whereas if a p-channel MOS transistor is to be fabricated, the diffusion layer including boron is formed. The thus formed diffusion layer 106 acts as a source/drain region.
Then, as illustrated in FIG. 1B, a titanium film 107 having a thickness of about 50 nm is deposited over a resultant by sputtering. Then, a resultant is thermally annealed for 30-60 seconds in N.sub.2 atmosphere under atmospheric pressure. In this thermal annealing, a lamp annealing apparatus is used, and process temperature is set in the range of 600.degree. C. to 650.degree. C. Thus, the titanium layer 107 is silicided.
As illustrated in FIG. 1C, on an exposed surface of the gate electrode 104 and also on the diffusion layer 106 are formed a C49-structure silicide layer 108 having a crystal structure and high resistivity, a first nitrogen containing silicide layer or a C49-structure silicide layer 109 containing nitrogen atoms therein, and a nitrided titanium nitride layer 110 in this order. On the other hand, on the device isolation insulative films 102 and the spacer 105 both composed of a silicon dioxide film are formed the titanium nitride layer 110 and a unreacted titanium layer 111.
Then, as illustrated in FIG. 1D, the unreacted titanium layer 111 and the titanium nitride layer 110 are removed by means of mixture solution composed of aqueous ammonia, pure water and hydrogen peroxide. It should be noted that the unreacted titanium layer 111 is dissolved in the mixture solution, but the titanium nitride layer 110 is not dissolved in the mixture solution. However, the titanium nitride layer 110 can be removed by lift-off accompanied by dissolution of the unreacted titanium layer 111.
Through the above mentioned steps, the C49-structure silicide layer 108 and the first nitrogen containing silicide layer 109 are formed in self-aligning fashion only on the gate electrode 104 and the diffusion layer 106 constituting source/drain regions.
When necessary, a second thermal annealing is carried out for about 60 seconds in N.sub.2 atmosphere under atmospheric pressure. Similarly to the first thermal annealing, a lamp annealing apparatus is used, and process temperature is set at about 850.degree. C. As illustrated in FIG. 1E, the second thermal annealing causes the C49-structure silicide layer 108 to change into a C54-structure silicide layer 112 having crystal structure and also having low resistivity. Then, a second nitrogen containing silicide layer or a C54-structure silicide layer 113 containing nitrogen therein is formed over the silicide layer 112.
In the above mentioned prior method of fabricating a salicide configuration, as a silicide layer becomes thinner as the semiconductor device becomes smaller and smaller in size, two problems inherent to thin-film technique arise, which problems appear in particular when a silicide layer is to be formed of a thin titanium film. The two problems are as follows.
First, the titanium silicide layer, namely the above mentioned C49-structure or C54-structure silicide layer is not completely formed because The thermal annealing is carried out by means of the lamp annealing apparatus in which both nitirization process and silicidation process of titanium occur. Because, the nitrization process has greater speed than the silicidation process, if a thinner titanium layer is attempted, the titanium silicide layer will be thinner than attempted. Thus, a silicide layer is not completely formed.
Second, leak current is increased between a gate electrode and source/drain regions because it is difficult to remove a titanium nitride layer on both the spacer and device isolation insulative which are films both composed of a silicon dioxide layer.
Hereinbelow will be explained these problems in detail from a technical viewpoint.
The first mentioned problem is as follows. It is necessary for a silicide layer to be selectively formed only on a gate electrode and a diffusion layer in a salicide configuration. In a conventional method of forming a silicide layer, silicon atoms are diffused in a refractory metal layer such as titanium, thereby silicidation makes progress. When silicidation proceeds on a spacer or a device isolation insulative film both composed of a silicon dioxide layer, silicon atoms contained in a diffusion layer or a polysilicon layer also diffuse into the pacer and the device isolation insulative film, forming a silicide layer where the silicon atoms are diffused (hereinafter, such phenomenon is referred to as overgrowth). Thus, it is not possible to selectively form a silicide layer. In order to avoid the overgrowth from occurring, it is necessary to lower the temperature of the above mentioned thermal annealing.
In such lowered temperature, the nitrization speed of titanium is greater than the silicidation speed of titanium, as having been mentioned earlier. Thus, only the titanium nitride layer and almost no silicide layer is formed on a gate electrode and a diffusion layer.
The secondly mentioned problem is as follows. As mentioned earlier, a titanium nitride layer is formed on a spacer and/or a device isolation insulative film. If a titanium film has a small thickness, the titanium film is entirely changed into a titanium nitride layer by the thermal annealing, and thus no titanium remains film. Thus, it is not possible to completely remove the titanium nitride layer having been formed on a spacer and/or a device isolation insulative film a by lift-off process in which the above mentioned mixture solution is used. Accordingly, an electrical path is formed from residual titanium nitride for current to run between a gate electrode and a diffusion layer, and hence, leak current is increased between a gate electrode and source/drain regions, as mentioned earlier. If etching is carried out sufficiently long to completely remove the titanium nitride layer by using the above mentioned mixture solution, the silicide layer having been formed on a gate electrode and/or a diffusion layer is also removed, resulting in increased electrical resistance.
U.S. Pat. No. 4,855,798 issued to Imamura et al. on Aug. 8, 1989 also discloses a method of fabricating a semiconductor device having a salicide configuration. The method includes the steps of preparing a semiconductor substrate, forming a silicon layer on the substrate, forming a metal layer on the silicon layer, and heating the resultant structure in the presence of a reaction ambient containing nitride for forming a metal silicide layer on the silicon layer and nitriding a surface portion of the metal silicide layer to form a nitride layer consisting of a nitride of the metal silicide.
U.S. Pat. No. 4,545,116 issued to Lau on Oct. 8, 1985 discloses a method of forming a metallic silicide on silicon or polysilicon in which a masking layer, such as silicon dioxide, is formed on a silicon slice and patterned to expose selected areas of the slice surface. The slice is then sputter etched followed by in situ deposition of a metal layer. The slice is heated to convert the portion of the metal layer in contact with the silicon and/or polysilicon to a metal silicide, then the non-converted metal is removed by a selective etchant.